An arrangement using a DLL (Delayed-Locked Loop) of the kind shown in FIG. 18 is known as a circuit that generates a signal having a prescribed phase with respect to an input signal. With regard to the arrangement shown in FIG. 18, see Reference 1 (ISSCC 1997 pp. 332–333, S. Sidiropoulos and Mark Horowitz et al., “A Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08–400 MHz Operating Range”).
As shown in FIG. 18, the DLL has an input buffer 11, a voltage-controlled delay line 14, a phase comparator 12 for detecting a phase difference between an output signal of the voltage-controlled delay line 14 and an output signal of the input buffer 11, and a filter 13 for smoothing a phase-difference detection signal output from the phase comparator 12. The voltage-controlled delay line 14 comprises a plurality of cascade-connected buffers. The phase comparator 12 is constituted by, e.g., a D-type flip-flop. The voltage-controlled delay line 14 is supplied with a voltage obtained by integrating the output signal of the phase comparator 12 by the filter 13, which includes a charge pump and an RC filter for converting the output signal of the phase comparator 12 to a voltage signal. The delay time in the voltage-controlled delay line 14 is variably set and feedback control is performed in such a manner that the phase of the output of input buffer 11 and the phase of the output of voltage-controlled delay line 14 will coincide (i.e., so that the phase difference between them will become zero). The multiple buffers of the voltage-controlled delay line 14 produce output clocks of equally spaced phase differences.
FIG. 19 illustrates a clock control circuit that produces a multi-phase clock by replacing the voltage-controlled delay line 14 of FIG. 18 with a variable oscillator circuit 15 such as a VCO (Voltage-Controlled Oscillator). With regard to the arrangement shown in FIG. 19, see Reference 2 (ISSC 1993 pp. 160–161, Mark Horowitz et al., “PLL Design for a 500 MB/s Interface”). FIG. 19 schematically illustrates one part of the main loop of a PLL circuit described in Reference 2. The variable oscillator circuit 15 such as a VCO produces a plurality of clock outputs (e.g., a plurality of clock outputs of equally spaced phase differences) and supplies these to transmit and receive fine loops (not shown) so that the phase of the internal clocks undergoes fine adjustment.
The arrangements shown in FIGS. 18 and 19 have a feedback loop constituted by a DLL or PLL and exhibit phase jitter ascribable to the feedback loop. This makes it difficult to generate correctly a signal of a desired phase. The present invention has been devised in view this problem.